1. Technical Field
The present invention relates generally to cache memories, and more particularly to an integrated circuit memory especially adapted for performing cache memory functions. Specifically, the present invention relates to an integrated circuit including high speed memory, a lower-speed memory of greater capacity, and interconnecting data path circuits for constructing a hierarchical cache memory.
2. Description of the Background Art
In the field of high speed computing, processor speed is generally limited by memory performance. For example, a central processing unit (CPU) executes instructions at a predetermined rate. Similarly, main memory performs read and write operations at a second predetermined rate which is typically at least an order of magnitude slower than the CPU execution rate. If the CPU were to access the main memory directly during the execution of memory access instructions, the CPU performance would degrade to the memory access rate. In this case the CPU would have to stall while waiting for the main memory to complete its access cycle for each memory access instruction.
It is possible to construct a special purpose memory which has a cycle time approximately equal to that of the CPU's instruction cycle time. Unfortunately, such special-purpose memories use high-speed static random access memory (RAM) which is far more expensive than the typical dynamic RAM used in main memory. Accordingly, many computer systems compromise by constructing a relatively small cache of high-speed memory while retaining the slower semiconductor memory in the main memory.
The cache is managed under hardware control to maintain a copy of a portion of the main memory contents which is likely to be used by the CPU. Thus, as long as the CPU accesses only those memory locations maintained in the cache, the CPU will execute at full speed. Of course, it is inevitable that the CPU will occasionally attempt to read a memory location which is not contained in the cache. During these misses, the data are retrieved from main memory and stored in the cache. Therefore, CPU performance degrades to the main memory access rate during misses, but the misses are relatively infrequent so that the overall speed of the processor is enhanced by the use of the high-speed cache.
In recent times, processors have been introduced that have execution cycle times below the access times of typical static RAM memories. These processors, for example, have cycle times under 10 nanoseconds. Because such a fast execution speed is poorly matched to the access time of static RAM cache memories, these processors are designed with "on-chip" cache memories that provide an additional level of memory between the processor and the cache memory. The on-chip cache memories eliminate inter-chip data transmission delay, but they are necessarily limited in storage capacity to much less that the capacity of a single chip containing just high-speed memory. Therefore the relatively high miss rate of the on-chip cache tends to limit substantially processor performance, in view of the disparity between the execution speed of the CPU and the access time of the static RAM cache.
The speed disparity between the high-speed processor and static RAM cache memory has encouraged cache designers to place a "primary" cache of very high speed memory between the processor and the "secondary" static RAM cache. The construction of such a "hierarchical" cache memory, however, has been impractical due to the huge number of input/output lines and the associated buffers and multiplexing circuitry required for interfacing the secondary cache memory with the main memory and the primary cache memory, and the need for keeping the primary and secondary cache memories in close proximity to the processor to minimize signal transmission delay.